An embedded flash storage device (such as an embedded flash storage device) is a flash storage device that is embedded in a computerized system that also includes a host computer and a flash memory controller. The embedded flash storage device may be activated only under the permission of the host computer.
Data units can be read from the embedded flash storage device during read transactions and can be written (programmed) to the embedded flash storage device during write transactions.
The read and write processes utilize one or more memory management tables that may map logical addresses of data units to physical addresses of flash memory cells that store the data units.
The embedded flash storage device are subjected to power failures but are expected to maintain the integrity of data units that were written during successfully completed write transactions despite such power failures.
In order to maintain this integrity a successfully completed write transaction should include the programming of (a) data unit, and of (b) one or more memory management tables that are updated to reflect the programming of the data unit.
The throughput of an embedded flash storage device is inversely proportional to the latency of a transaction.
Referring to a write transaction latency—this latency is defined by a period required to successfully complete a write transaction—including a programming of one or more data units and a programming updated memory management tables (after updating the memory management tables).
FIG. 1 illustrates a prior art timing diagram 10 and FIG. 2 illustrates a prior art method 20.
The method 20 includes the following sequence of stages starting (21) by a flash memory controller, a write transaction; programming (22), by the embedded flash storage device, a data unit to a flash memory unit of the embedded flash storage device; updating (23) by the flash memory controller, the memory management tables to reflect the programming of the data unit; programming (24) by the embedded flash storage device, the memory management tables (after being updated) to the flash memory unit; sending (25) to the host computer an acknowledgement of a successful completion of the write transaction—after a successful completion of stages 21-24; sending (26) the write transaction.
It is noted that stages 22 and 24 are relatively long in relation to other stages of method 20.
Timing diagram 10 illustrates the sequence of signals and stages a write transaction initialization signal 11 from the host computer to the flash memory controller. This starts a write transaction of duration 12; initial operations (13) executed by the flash memory controller before the programming of a data unit. This may include determining where to write the data unit, error correction encoding the data unit and the like; programming (14) by the embedded flash storage device, a data unit to the flash memory unit of the embedded flash storage device; intermediate operations (15) executed by the flash memory controller before programming the memory management tables—such as updating the memory management tables; programming (16) the memory management tables to the flash memory unit; final operations (17) executed by the flash memory controller. For example—checking the status of a program; sending (18) an acknowledgment to the host computer and thereby ending the transaction.
As illustrated above—the host computer can be notified that the write transaction succeeded only after the (entire) write transaction succeeded and thus the latency of write transaction is relatively high and the throughput of the embedded flash is low.
There is a need to provide a low latency and power failure tolerant method for programming data units to an embedded flash storage device.